An integrated circuit or circuit assembly generally contains one or more clocks, either generated internally or controlled externally. Each clock is distributed to a set of storage cells via a skew-minimized network, which delivers a clock pulse to all the storage cells at virtually the same time. Such a clock, its related storage cells and all combinational logic blocks bounded by the storage cells, form a clock domain.
Scan testing of circuits is well known and is the most widely used design-for-test (DFT) technique used to test integrated circuits. It replaces all or part of original storage cells with scan cells that may be linked to form one or more scan chains. A scan-based integrated circuit or circuit assembly can be tested by repeating a shift cycle followed by a capture cycle. In a shift cycle, pseudorandom or predetermined test stimuli are shifted into all scan chains, making their outputs as controllable as primary inputs. In a capture cycle, test responses are latched into some or all scan chains, making their inputs as observable as primary outputs, because the values captured into scan chains can be shifted out in the next shift cycle.
Scan based tests are expensive because of the high capital investment in test equipment and because they can require a considerable amount of time to run. Test times for scan based tests depend on how fast the test is being run and the volume of the test, e.g., the magnitude of the test pattern. Due to high demands to reduce test costs of scan based tests and optimize turn-around time for integrated circuit releases, scan shift operations need to be run at increasingly higher clock speeds. Usually scan shift operation test times are 50% to 75% of the total test time required for the chip.
Running scan shift operations at higher clock speeds helps in reducing the overall test time. However, it can cause power issues resulting in flip-flops and gates behaving incorrectly under inadequate power supply conditions. This could cause false failures due to the electrical and thermal stressing of the silicon under test, which could result in significant yield loss. Accordingly, users of the test system are left with no other alternative but to slow down the clock speeds in order to minimize power related issues, which results in longer test times.
For example, during a shift cycle all the test stimuli are shifted into the flip-flops simultaneously, thereby, causing all the flip-flops on the chip to switch at the same time. This causes a substantially high peak current resulting in a voltage drop from the power rails due to rail resistance. Because of the voltage drop resulting from the peak current demand, the voltage supplied to the chip is not within the expected operating range of the chip, which may cause it to malfunction. Also, the flip-flops on the chip will eventually start failing if the scan shift operations continue to be run at these high operating frequencies. As compared to scan shift mode, running the chip at higher frequencies during normal functioning mode is not problematic because not all the flip flops are expected to switch at the same time during normal functional mode.
Further, the dynamic power consumption during scan test, with and without test compression, is always higher than the functional mode because of very high toggling rates and logic activity during scan shift operations. Exceeding the peak power for which the chip and package have been designed can result in excessive heat dissipation during testing that can damage the package. This increased dynamic power consumption can cause reliability issues in chips, which may result in the chip subsequently failing in the field.